The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Another aspect of the IC evolution involves increased IC design complexity and shortened time-to-market. Designers generally face a demanding project schedule from IC conception to IC production. To meet these challenges, designers generally perform simulations on an IC design, and check the performance and functionality of the IC design as thorough as possible before taping it out. A realistic simulation takes into account of variations in device properties across an entire area of the IC. Such variations are commonly referred to as on-chip variation (OCV). OCV in a fabricated IC may be caused by factors such as channel length variations among transistors; hot spots in the IC; variations in interconnect lengths; and so on. A typical OCV modeling uses local variations, assuming a fixed percentage change of circuit property (e.g., propagation delay) for timing analysis. However, it has been found that local variations are not a fixed value across the entire area of an IC chip, and are in fact a function of distances among the devices (such as transistors). This phenomenon is called OCV spatial effects.
To obtain more realistic IC simulations, attempts have been made to model OCV spatial effects by creating spatially correlated random variations in device properties. Such random variations must simultaneously satisfy correlation constraints between all pairs of devices. As the number of devices on an IC increases, this task has become increasingly challenging.
Accordingly, what is needed is improvement in this area.